The present invention generally relates to non-volatile memory devices and methods of fabricating the same and, more particularly, to phase-changeable memory cells and methods of fabricating the same.
Non-volatile memory devices typically retain their stored data even when their power supplies are interrupted. Many non-volatile memory devices use flash memory cells having a stacked gate structure. The stacked gate structure typically includes a tunnel oxide, a floating gate, an intergate dielectric, and a control gate electrode. Improving the tunnel oxide and increasing a cell coupling ratio may enhance reliability and programming efficiency of the flash memory cells.
New non-volatile memory devices, referred to here as phase-changeable memory devices, have been proposed as a replacement for flash memory devices. Phase-changeable materials have at least two stable states, which may be achieved using temperature variation. For example, if a phase-changeable material is cooled after being heated to a temperature higher than a melting temperature, it may achieve an amorphous state. On the other hand, if the same phase-changeable material is cooled after being heated to a temperature higher than a crystallization temperature but lower than the melting temperature, it may achieve a crystalline state. A resistivity of the phase-changeable material layer in the amorphous state may be higher than in the crystalline state, and the variance in resistance may be used to discriminate between a logic “1” or logic “0” in a phase-changeable memory cell.
Reducing a contact area between an electrode and a phase-changeable material to enhance efficiency of a phase-changeable memory device is described in U.S. Pat. No. 6,117,720 entitled “METHOD OF MAKING AN INTEGRATED CIRCUIT ELECTRODE HAVING A REDUCED CONTACT AREA”.
FIG. 1 is a cross-sectional view of a typical conventional phase-changeable memory device. The illustrated conventional phase-changeable memory device includes a bottom electrode 60 formed on a semiconductor substrate and an interlayer dielectric 50 disposed on the bottom electrode 60. A plug 42 is disposed within an opening in the interlayer dielectric 50 and is electrically connected to the bottom electrode 60. Spacers 44 are formed on sidewalls of the interlayer dielectric 60 in the opening and on the plug 42. A contact 46 is formed between the spacers 44, in contact with the plug 42. The contact 46 may be made of a phase-changeable material or a conductive material. If the contact 46 is made of a conductive material, a phase-changeable layer 62 may be formed on the interlayer dielectric 50 and the contact 46.
Such a conventional phase-changeable memory device has a stacked structure and may, therefore, provide the advantages of a smaller occupied area and a higher integration density. However, a stress may be generated at or near the contact area between a conductive material and a phase-changeable material that may degrade phase-changeable characteristics. The phase change is generally accomplished using heat generated by current passing through the contact resistance of the phase-changeable material and the conductive material. However, heat may be dissipated at or near a boundary 48 of the contact area resulting in an unsatisfactory phase change.
For example, referring to FIG. 2, when current flows through the contact 46 and the bottom electrode 60, heat may be generated at or near a boundary between the contact 46 and the phase-changeable layer 62 due to contact resistance at the boundary. The heat may change the state of the phase-changeable material in a region PC. However, heat e may sometimes be dissipated or lost at or near the boundary resulting in an unsatisfactory phase change. Unsatisfactory phase changes may result in inaccurate data storage.